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NXP Semiconductors /MK64F12 /GPIOE /PTOR

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Interpret as PTOR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PTTO0 0 (0)PTTO1 0 (0)PTTO2 0 (0)PTTO3 0 (0)PTTO4 0 (0)PTTO5 0 (0)PTTO6 0 (0)PTTO7 0 (0)PTTO8 0 (0)PTTO9 0 (0)PTTO10 0 (0)PTTO11 0 (0)PTTO12 0 (0)PTTO13 0 (0)PTTO14 0 (0)PTTO15 0 (0)PTTO16 0 (0)PTTO17 0 (0)PTTO18 0 (0)PTTO19 0 (0)PTTO20 0 (0)PTTO21 0 (0)PTTO22 0 (0)PTTO23 0 (0)PTTO24 0 (0)PTTO25 0 (0)PTTO26 0 (0)PTTO27 0 (0)PTTO28 0 (0)PTTO29 0 (0)PTTO30 0 (0)PTTO31

PTTO1=0, PTTO19=0, PTTO18=0, PTTO4=0, PTTO7=0, PTTO24=0, PTTO13=0, PTTO2=0, PTTO9=0, PTTO12=0, PTTO22=0, PTTO3=0, PTTO10=0, PTTO0=0, PTTO23=0, PTTO16=0, PTTO11=0, PTTO5=0, PTTO6=0, PTTO26=0, PTTO27=0, PTTO30=0, PTTO20=0, PTTO31=0, PTTO28=0, PTTO21=0, PTTO29=0, PTTO25=0, PTTO15=0, PTTO14=0, PTTO17=0, PTTO8=0

Description

Port Toggle Output Register

Fields

PTTO0

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO1

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO2

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO3

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO4

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO5

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO6

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO7

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO8

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO9

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO10

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO11

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO12

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO13

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO14

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO15

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO16

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO17

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO18

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO19

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO20

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO21

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO22

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO23

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO24

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO25

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO26

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO27

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO28

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO29

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO30

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.
PTTO31

Port Toggle Output

0 (0): Corresponding bit in PDORn does not change.

1 (1): Corresponding bit in PDORn is set to the inverse of its existing logic state.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data